Premananda B S

The various security protocols in wireless sensor networks (WSNs) provide confidentiality for the content of message but the contextual information remains exposed. The exposed contextual information can be utilized by the adversary to deliver attack or derive the sensitive information such as location of the sink nodes, source node and monitored objects. In sensor network the base station (BS) acts as a gateway between the sensor nodes and the control unit. By known information of the physical location of the BS the attacker can alter or destroy the BS intern results that cause the failure of the entire sensor network. There is a need for routing algorithm which can effectively camouflage the location of the BS. In this paper a hybrid algorithm that provides location privacy of the BS has been proposed. The results infer that the proposed algorithm is independent of quantity of the traffic and an adversary will have less than 4 % chance of locating the physical location of the BS. The sensor nodes also exhibited limited energy consumption. � 2019, Institute of Advanced Scientific Research, Inc.. All rights reserved.

The CMOS technology is recognized for high levels of integration and low power dissipation. Portable devices usually operate on batteries with minimal charge storage capacity. Power consumption is the limiting factor for the functionality offered by portable devices that operate on batteries. This has made researchers explore for new techniques to recover the energy from the circuit. One of the efficient ways to reduce the power consumption of the circuits is to design the circuit using adiabatic logic. Shifters are one of the basic elements of digital signal processors and are used for manipulating the data. Shifters are used to efficiently perform division and multiplication operation on unsigned integers by powers of two. There exist two types of shifters, viz. combinational and sequential Shifters. The paper focuses on the design of power efficient 8-bit combinational shifter, namely barrel shifter using positive feedback adiabatic logic (PFAL). Also, a comparison is performed with the conventional static CMOS barrel shifter using multiplexer logic and pass transistor logic. Cadence Virtuoso is used for the implementation with CMOS 180 nm technology, and Cadence Spectre simulator is used for simulation and functional verification. The analysis of the logic circuits infers that PFAL-based barrel shifter consumes the least power. The power values infers that PFAL technique is advantageous when applied to low-power digital devices operated at relatively low frequencies. � 2020, Springer Nature Singapore Pte Ltd.

Quantum Dot Cellular Automata (QCA) is a layout level tool used for designing digital logic circuits at nano scale. It can be regarded as the substitute for CMOS technology in nano-scale. Designing decoders in nano scale (QCA) provides advantages such as effective area utilization, energy dissipation and cost. The aim of the paper isto minimize the number of cells, area, cost and the cost energy dissipation in decoders. This paper presents a cost effective and compact design for QCA based 2 to 4 and 3 to 8 decoders. The paper proposes a design for the decoders in a multi-cell layer structure with appropriate energy dissipation analysis. The proposed 2 to 4 decodercircuit has achieved an overall improvement of 29.57% in terms of cell count and an improvement of 68.8% in cost function compared to reference circuit. The proposed 3 to 8 decoder circuit has a reduction of 53.8% in total cell count and 59.25% in terms of cost function w.r.t the earlier proposed circuits. The energy analysis is performed by QCADesigner-E tool and the circuit isrealized in QCADesigner 2.0.3 CAD tool. The proposed decoder is pre-eminence compared to reference decoder in terms of cost, cell count, area andenergy dissipation. � 2021 IEEE.

The technology has grown at an ultra-fast pace along with the world where many of the automotive applications use Controller Area Network (CAN). A CAN interconnects a node or module using two wires or twisted pair cable which acts as data bus to communicate between any systems. For the data to be sent and received, total amount of data is needed and the bandwidth analysis of the data bus is required to know the utilization of the CAN bus. This paper discusses about the CAN bus and a method to analyse the data sent in a CAN bus. Further, a bandwidth analysis is performed for the analysed data to know the utilization of the data bus. The data transmission in CAN bus for a particular period is analysed graphically and also the analysis of bandwidth utilization. The CAN bus is implemented in MATLAB 2016b. The bus speed for CAN bus was chosen as 250 Kbps out of which only 40.876 Kbps was found to be used which is only 16.35% of the entire bus. � 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

A cloud-native application hosted in the cloud and are designed to capitalize on the inherent characteristics of a cloud computing software delivery model. Applications that are cloud-native use a microservice design, which effectively distributes resources to each service they require, allowing them to be flexible and adaptive to a cloud architecture. This paper discusses cloud native approach in detail and compares with the traditional approach to designing, building and deploying applications and highlights the need to switch to cloud native. The four major components of Cloud native architecture are microservices, devops, continuous delivery and containers. The various factors to consider during the design of a cloud native application and the development stack required to do so, are also discussed in detail. Tools such as the 12 factor application, API based design, and microservices, which are essential for cloud native applications, are examined. Some of the other challenges that come with cloud computing are resolved by cloud-native applications. Cloud native solutions, from an economic perspective, provide the full value of the cloud by enabling applications to scale and change more quickly than before. This scalability gives the company new chances to grow their revenue, become more efficient, or provide better customer service. � 2022 IEEE.

In mobile communication systems, deterioration in intelligibility of the voiced content of the signal is a commonly observed phenomenon. In order to counter the undesirable effect of background noises on the speech signal, a methodology must be developed such that there is no loss in intelligibility of the speech signal.Thiswork focuses on developing an approach to attain enhancement of speech critical band-wise, when the near-end noise dominates. Two different approaches are employed for speech enhancement. First approach involves enhancing the lower critical bands while the second approachincludeshigher critical band enhancement. The intelligibility is measured in terms of Speech Intelligibility Index (SII). The SII values infer an improvement in speech intelligibility for higher critical band enhancement. � 2016 IEEE.

Power dissipation is a significant issue in many digital and VLSI systems. Adiabatic logic is a promising technique in minimizing the power dissipation, and positive feedback adiabatic logic (PFAL) proves to be efficient. The arithmetic operations in the digital systems are incomplete without the use of adders and multipliers. In this paper, a 16-bit square root carry select adder (SQRT CSLA) is implemented using ripple carry adder (RCA). The limitation of power and area in SQRT CSLA using RCA is overcome by incorporating Binary to Excess-1 Converter (BEC) in place of RCA. An 8� �� 8 Wallace tree multiplier (WTM) is implemented using the concept of carry-save addition. The limitation of area in WTM is overcome by implementing reduced complexity WTM (RCWTM). The adders and multipliers are realized in both static CMOS and PFAL in Cadence Virtuoso 180� nm technology and simulated in Spectre. The static CMOS-based SQRT CSLA using BEC dissipates 50.25% less power as compared to SQRT CSLA using RCA which makes SQRT CSLA using BEC a better choice w.r.t. power dissipation and area. The PFAL-based SQRT CSLA using RCA and SQRT CSLA using BEC dissipates 54.5 and 83.5% less power as compared to static CMOS designs. PFAL-based RCWTM dissipates 81.8% less power than the static CMOS design. Circuits designed using PFAL dissipates less power as compared to those designed using static CMOS logic with a tradeoff in area. � 2019, Springer Nature Singapore Pte Ltd.

A wireless sensor network (WSN) is an independent network comprising of huge number of sensor motes and base stations (BS). Security is a major concern in military forces and border surveillance. BS which collects information from sensors has become the main target of attack for intruders. Anonymous intruder eavesdrops into network, analyzes the radio patterns to get contextual information, and can find where the BS location is. Attacker can destroy BS or alter its behavior which results in malfunctioning or complete failure of the entire network. In this paper, a hybrid algorithm for the BS anonymity has been proposed which provides protection for the sink node against adversaries. By making the BS anonymous in the network, it will be difficult for any intruder to find the location of the BS. The proposed algorithm is developed and simulated in MATLAB. The results infer that the anonymity of BS is independent of traffic volume and the algorithm proposed is efficient with varying locations of the sensor nodes. The anonymity value of BS for each topology is below 0.04. This infers that for the topology simulated an intruder conducting the traffic pattern analysis of WSN considered have a less than 4% probability of detecting the BS on the first trail when searching for physical location for the BS. � 2019, Springer Nature Singapore Pte Ltd.

Quantum-dot Cellular Automata (QCA) is a new age technology known for its low energy consumption and high clocking speeds. Serial Concatenated Convolution Coding (SCCC) is a class of Forward Error Correction (FEC) which is an error correction method where redundant bits are added to the data to ensure secure transmission. The SCCC encoder comprises of three stages and is implemented using the bottom-up approach where different stages are implemented and then are integrated. A compact QCA-based design of SCCC encoder has been proposed in this paper, which is efficient than the reference SCCC encoder in terms of cell count, the total area occupied, and energy dissipation. The SCCC design is proposed after analyzing the existing architecture by reusing the cells and optimizing the architecture. The SCCC encoder is designed using QCADesigner 2.0.3, and QCADesigner-E is used to calculate the energy dissipation. � 2022, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

Communication Protocols play a vital role in the functioning of various communication systems. LIN is cheaper compared to other communication protocols and is used wherever low costs are essential and speed is not an issue. To enable cold start in case of diesel engines, the cylinders are fitted with glow plugs to preheat the cylinder. The signals for controlling the GLPs are sent using LIN bus from the ECUs. This paper involves design and implementation of LIN 2.1 driver for RL78 microcontroller and configuration of IDs for communication of messages between ECU and the driver. The driver is designed to operate in slave mode with fixed baud rate as per SAE standards and incorporates sleep mode and error handling capability. Embedded C codes are written for various modules and are compiled using IAR Embedded Workbench. The functionality of driver is tested using the CANalyzer tool. � Springer Nature Singapore Pte Ltd. 2018.