Publication

Computational speed of basic data path elements such as adders plays a crucial role in performance of digital and signal processing systems. Among various adder architectures, carry select adder (CSLA) has better performance in terms of speed in comparison with others. However, this merit is accompanied by its high power dissipation and area occupancy due to redundant computing elements used in each stage hence limiting its application. Power dissipation in these adders can be minimized by various low power implementation techniques such as reversible logic gates, multi-Vth approach, and adiabatic logic. Among these low power approaches, adiabatic logic proves to be more efficient in comparison with other low power approaches. In the proposed work, 180 nm CMOS technology in CADENCE environment is used to carry out the design and analysis of both conventional and proposed CSLA architectures. Power dissipation in this proposed 8-bit CSLA architecture reduces by about 82% as compared to conventional 8-bit CSLA adder architecture. Further, the computational delay is also reduced when compared with the conventional 8-bit CSLA architecture. It is noteworthy that delay in adiabatic logic circuits greatly depends on frequency of operation [1]. � 2017 IEEE.

Static Random-Access Memories (SRAM) is the popular choice for memory. As the memory requirement increases, so does the power consumption. Quantum-dot Cellular Automata (QCA) is the technology for low energy, compact and faster digital circuits. The paper aims to design, implementation and performance analysis of compact 4�8 bit SRAM array. First, basic gates are realized in QCA and then one-bit memory cell is constructed. The optimized 4�8 bit SRAM is realized and simulated using QCADesigner with QCA cells of 18nm cell width and height. The proposed QCA memory cell has a cell count of 41 QCA cells; this is very less compared to QCA memory cells in literature. The proposed 4�8 bit SRAM array has a total QCA cell count of 3823, with one clock cycle delay for read/write operation, occupies area of 4.1 ?m2 and energy dissipation is 1.32 eV, as measured using QCA Designer-E. � 2020 IEEE.

The demand for low power devices is exponentially increasing with the increase in the use of portable equipment such as laptops and mobile phones. Adiabatic logic is an emerging technique which proves to be efficient in reducing the power dissipation of the system. Positive Feedback Adiabatic Logic (PFAL) is an efficient adiabatic logic. Multipliers are the fundamental arithmetic operators in the digital circuits. Addition is the integral part of multiplication, to add the partial products. A 16-bit Wallace Tree Multiplier (WTM) is implemented using carry-save addition. The Conventional WTM (CWTM) is modified to minimize complexity, termed as Reduced Complexity WTM (RCWTM) which has minimum number of Half Adders compared to the CWTM, which results in the reduction of the WTM area. The RCWTM is designed using both static CMOS logic and PFAL. The design is analyzed in Cadence Virtuoso 180 nm technology and simulated in Cadence Spectre. The PFAL based RCWTM dissipates 81.8% less power compared to static CMOS design. � 2020, Springer Nature Singapore Pte Ltd.

The importance of adaptive algorithms to recognize the existence of an interference is increasing since the adaptive antennas adjust the pattern automatically. One such adaptive algorithm is the least mean square (LMS), where the SNR of the required signal is optimized in the specified direction. The LMS adaptive algorithm is achieved by directing the beam toward the desired direction and generation of complex weights. This paper shows the need for the LMS algorithm to suppress the interference and the implementation of the algorithm on uniform planar arrays of size 8 � 8 with interelement spacing ?/2 and at subarray level. In subarray level, the 8 � 8 planar array is divided into 2 � 2 subarrays. � 2021, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

With the growth of the population in urban areas, the number of vehicles is also increasing in the cities. There is a growth of electronic complexity inside an intelligent vehicle and the diagnosis and reprogramming methods have to be improved. With increasing complexity of electronic systems in vehicles, the need for frequent and extensive software updates are increasing. These updates are important for the maintenance and enhancement of the software components. There is also an increase in bugs in the vehicles. This calls for upgrades for the ECU software and improved security functions. As the upgrades increase, the time for updating the ECUs also increase. The software update time also depends on the size of the data update. This paper presents the overview on ECU reprogramming, different reprogramming methods, the delta method of reprogramming with its advantages and the ECU communication. � 2021 IEEE.